1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to integrated circuits that include active components and at least one passive component and methods of fabricating such integrated circuits.
2. Description of Related Art
A DRAM cell consists of a control MOS transistor T and a storage capacitor C connected in series between an electrical ground M and a bit line BL, as shown in FIG. 1. The gate of the control transistor T is connected to a word line WL. The transistor T controls the flow of electrical charges between the capacitor C and the bit line BL. The electrical charge in the capacitor C determines the logic level (1 or 0) of the memory cell. When the memory cell is read, the capacitor C is discharged into the bit line BL. For fast and reliable reading of the value of the electrical charge in the storage capacitor C, the capacitance of the capacitor must be high compared to the capacitance of the bit line BL during the reading phase.
A large number of such DRAM cells are assembled in the form of a matrix to generate a memory plane that can include millions of individual cells. In some applications, the memory plane is within a complex integrated circuit. It is then referred to as an “onboard memory”.
There are many ways to make the storage capacitors of the such cells of an onboard memory. In the context of integrated circuits using sub-micron MOS transistors and including an onboard DRAM plane, it is generally preferred to produce the components of the integrated circuit in the substrate first and then to produce the storage capacitor C on top of the active components, before the levels of metal interconnections. This production sequence is the most efficient for maximizing the integration density of the integrated circuit components. Thus, the whole of the surface of the silicon of the memory plane can be used for the control transistors with the electrodes of the storage capacitors grown in the height-wise direction to increase the capacitance of each capacitor.
Each storage capacitor generally consists of two conductive plates (e.g., made of doped polycrystalline silicon) separated by a dielectric layer whose thickness is on the order of 20 nm. To produce this kind of storage capacitor, one plate of the capacitor is connected to one junction of the control MOS transistor T, as shown in FIG. 1. An ohmic contact can be established between the polycrystalline silicon constituting one plate of the storage capacitor and a doped monocrystalline silicon region if the two areas have the same type of conductivity.
A conventional storage capacitor of a cell of an onboard DRAM plane will now be described in more detail. FIG. 2 shows in cross-section one example of a conventional integrated circuit including, in the right-hand part, an N-type MOS transistor 1 and, in the left-hand part, a capacitor 2 that can be used as a storage capacitor in a cell of an onboard DRAM plane. Such an integrated circuit is generally produced in the following manner.
Shallow trenches 7 filled with an insulating material are formed in a P-type monocrystalline silicon substrate 3. Monocrystalline silicon active areas 5 and 6 between the trenches are flush with the surface of the substrate. An oxide 8 is formed on the surface of the substrate and polycrystalline silicon 10 is deposited on the surface of the oxide 8. The polycrystalline silicon 10 is then etched so as to produce the control gate of the MOS transistor 1 as well as that of the other MOS transistors of the integrated circuit.
N-type dopants are implanted in a conventional manner. The implantation is masked by the polycrystalline silicon 10 so that only the uncovered portions 5a and 6a of the active areas 5 and 6 are converted into N-type silicon. A doping level (denoted “N” in FIG. 2) greater than 5×1019 at/cm3 is obtained in the uncovered areas 5a and 6a, which is propitious for forming ohmic contacts. Two insulating layers 12 and 13 are then deposited successively and are such that they can be selectively etched relative to each other. A chemical and mechanical polishing (CMP) step produces a plane surface on the external insulating layer 13. A cavity 16 is formed in the insulating layer 13 and a contact hole 17 is formed between the bottom of the cavity 16 and the surface of the active area 6a. 
Polycrystalline silicon 18 is then deposited so that it fills the contact hole 17 and carpets the bottom and the sides of the cavity 16. The polycrystalline silicon 18 constitutes the first plate of the capacitor 2. It must be strongly doped to reduce spurious resistances, especially in the contact hole 17. The polycrystalline silicon 18 must have an N-type doping level of at least 5×1019 at/cm3 inside the contact hole 17. To this end, it is possible to deposit doped polycrystalline silicon in situ using the chemical vapor deposition (CVD) process. However, the dopant present during deposition greatly reduces the rate of deposition and therefore increases the cost of deposition.
Another method deposits undoped polycrystalline silicon and then dopes it by ion implantation. In this case the structure must be strongly annealed to ensure strong doping throughout the thickness of the layer and in particular in the contact hole 17. The thermal budget associated with such diffusion annealing (e.g., carried out at 950° C. for 20 minutes) may be incompatible with the production of MOS transistors with sub-micron dimensions. Additionally, the dopant of the polycrystalline silicon layer 18 must not penetrate into the active area of the underlying N-type monocrystalline silicon active area, as it would then enlarge and disrupt it. It is thus preferable to use arsenic as the dopant for the polycrystalline silicon. Arsenic has the property of not passing easily through the polycrystalline silicon/monocrystalline silicon interfaces. However, arsenic diffuses relatively little and the thermal budget must therefore be increased.
To complete the capacitor 2, an insulating deposit 19 (e.g., of silicon oxide or silicon nitride) is produced by the CVD process. A doped polycrystalline silicon layer 20 is then deposited on top of layers 18 and 19 to constitute the second plate of the capacitor 2. A CMP step eliminates any layers 18, 19, and 20 above the top surface of the insulating layer 13. One level of interconnection is then produced by carrying out the following steps. An oxide layer 30 is deposited and contact openings 31 and 32 are etched. Contact opening 31 opens onto one junction of the MOS transistor 1 and contact opening 32 opens onto the second plate 20 of the capacitor 2. The contact holes 31 and 32 are then filled with tungsten terminals 33 and 34. Finally, a metal 35 is deposited and etched to produce the first level of interconnection of the integrated circuit.
This conventional structure and fabrication process has many drawbacks. First, there are problems regarding ohmic contact between the polycrystalline silicon 18 constituting one plate of the capacitor 2 and the doped monocrystalline silicon region 6a. The resistance of the contact is high because polycrystalline silicon is resistive. Moreover, the efficiency of the contact is not very high because the technology for having direct contact between polycrystalline silicon and monocrystalline silicon is not in widespread use and the quality of the monocrystalline silicon/polycrystalline silicon interface is difficult to control and make reproducible. Additionally, with regard to the problems of efficiency, the contact surface area of the contact hole 17 is generally smaller than that of the corresponding diffusion 6a. The contact hole 17 does not extend right through and does not straddle the boundary between the active area 6a and the trench 7.
Major technological constraints are also encountered. For example, the etching of the insulating layer 13 must be selective relative to the insulating layer 12. This necessity for selectivity renders the choice of insulation critical or complicates the stacking of the insulating layers 12 and 13. The topology of the cavity 16, which is deep and narrow, makes it difficult to form the contact hole 17 at the bottom of the cavity. Furthermore, the deposition of the layer 18 constituting the first plate of the capacitor 2 is unreliable (in terms of contact quality), difficult, and costly. The relatively great thickness of the layer 18 at the location of the hole 17 constitutes an additional problem.
Further, contact hole 31 is very deep (a few micrometers) because it passes in succession through insulating layers 30, 13, and 12. The contact holes 31 and 32 have very different depths. This makes it technologically very difficult to produce this kind of contact with minimum design rules. The use of more severe design rules is therefore obligatory, and this increases the surface area of the integrated circuit.